1. Field of the Invention
The invention relates to integrated circuits, and in a particular example to a field effect transistor driver circuit with overcurrent protection.
2. Related Art
Modern power circuits typically incorporate one or more power transistors that are regulated to provide desired voltage and current outputs. Typically, such power transistors are field effect transistors (FETs) that are controlled by dedicated FET driver circuits.
For example, a low dropout voltage regulator (LDO) is a circuit used to minimize the difference between an input supply voltage and a regulated output voltage provided by a FET power transistor, in particular an NMOS power transistor. FIG. 1 shows an LDO 180 that includes an LDO input terminal 181, a sense resistor RS1, an NMOS power transistor Q182, output resistors RH1 and RL1, and a conventional FET driver circuit 100. Sense resistor RS1, power transistor Q182, output resistor RH1, and output resistor RL1 are serially connected between input terminal 181 and ground, and a load 190 is coupled to receive an output voltage VOUT from the source of power transistor Q182.
To ensure that the desired output voltage is provided by power transistor Q182, FET driver circuit 100 includes an error amplifier 110 and a bandgap reference 130. Bandgap reference 130 provides a reference voltage to the non-inverting input of error amplifier 110, while the output of error amplifier 110 is connected to the gate of NMOS power transistor 182. Meanwhile, the inverting input of error amplifier 110 is connected to a node A1 at the junction between output resistors RH1 and RL1.
Output resistors RH1 and RL1 form a voltage divider that is part of a feedback loop 102 for error amplifier 110. This feedback loop causes error amplifier 110 to adjust the gate voltage of transistor Q182 until the voltage at node A1 matches the voltage provided by bandgap reference 130. Therefore, a desired value for output voltage VOUT can be set by properly sizing output resistors RH1 and RL1.
To prevent excessive current flow through power transistor Q182 (and potentially through load 190), FET driver circuit 100 also includes a current limiting amplifier 120, a resistor R101, a current source CS11, and an NMOS control transistor Q102. Resistor R101 is connected between input terminal 181 and current source CS11, while control transistor Q102 is connected between the output of error amplifier 110 and ground. The inverting and non-inverting inputs of current limiting amplifier 120 are coupled to the output terminals (i.e., the terminals downstream in the nominal current path) of resistors RS1 and R101, respectively. Finally, the output of current limiting amplifier is connected to the gate of control transistor Q102.
Current source CS11 pulls a constant current through transistor R101, thereby creating a reference voltage drop between input terminal 181 and the non-inverting input of current limiting amplifier 120. The resistance of sense resistor RS1 is selected such that when the current flow through power transistor Q182 reaches a predetermined threshold (called an “overcurrent condition” herein), the voltage drop across sense resistor RS1 is greater than the reference voltage drop across resistor R101. Prior to the current flow through power transistor Q182 reaching the predetermined threshold, the voltage drop across resistor R101 is greater than the voltage drop across resistor RS1.
During normal operation of LDO 180 (i.e., non-overcurrent conditions), when the voltage drop across sense resistor RS1 is less than the voltage drop across resistor R101, the voltage at the inverting input of current limiting amplifier 120 is greater than the voltage at the non-inverting input of current limiting amplifier. Consequently, during normal operation, current limiting amplifier 120 generates a LOW output signal that keeps NMOS control transistor Q102 in an off state. The output of error amplifier 110 therefore controls power transistor Q182 by providing a voltage to the gate of power transistor Q182, and hence, controls the output of LDO 180.
However, as the current flow through power transistor Q182 approaches the threshold current (i.e., the overcurrent condition), the voltage drop across sense resistor RS1 begins to approach the reference voltage drop across resistor R101, which causes the output of current limiting amplifier 120 to being switching to a HIGH output. At the threshold, the voltage output from current limiting amplifier 120 is sufficient to turn on control transistor Q102, which pulls the output of error amplifier 110 towards ground, thereby turning off power transistor Q182 and reducing the output current flow. In this manner, conventional FET driver circuit 100 provides a simple control circuit for power transistor Q182 that includes overcurrent protection.
Unfortunately, the overcurrent protection provided by conventional FET driver circuit 100 can create undesirable output instability. Specifically, as current limiting amplifier 120 turns off NMOS power transistor Q182 in response to an overcurrent situation, the voltage at node A1, and therefore the voltage at the inverting input of error amplifier 110, decreases. However, the voltage provided by bandgap reference 130 to the non-inverting input of error amplifier 110 remains constant at the bandgap voltage. Therefore, error amplifier 110 will attempt to increase its output voltage, which is provided to the gate voltage provided to power transistor Q182, even as current limiting amplifier 120 is trying to reduce that gate voltage (via transistor Q102) in response to the overcurrent situation. This conflict between error amplifier 110 and current limiting amplifier 120 can lead to problematic oscillations of output voltage VOUT of LDO 180.
Accordingly, it is desirable to provide an improved method and apparatus for providing overcurrent protection.